Present-day integrated circuit (IC) chips have advanced significantly in both complexity and sophistication. For example, in early generation chip designs, a chip might embody relatively simple electronic logic blocks effected by interconnections between logic gates; whereas, newer generation chips include designs having combinations of complex, modularized IC designs often called “cores”, which together constitute an entire SoC. These newer generation IC designs increase the overall functionality and performance characteristics of the chip, itself, by, for example, having the ability to include smaller feature sizes and thus increasing the amount of circuitry which can be built on a single chip. But, this comes at a cost: longer design and verification times which, in turn, translate into added development and manufacturing costs.
The verification phase of chip design has moved toward a software simulation approach to avoid the costs of implementing designs in hardware to verify the workability of such designs. However, multiprocessor and multicore designs can lead to very large simulation models. Even when using modern simulation tools, simulation load and execution time, as well as build time can become cost and time prohibitive. This is especially true in complex design cases with inter-processor clusters since a complete gate level representation of the design must be constructed and loaded into the simulation for each processor.
As the chip design becomes more complex, the verification tends to require an even more inordinate amount of time and computing resources, largely due to the modeling and verification of the interaction of functions associated with the design. This verification process becomes more complicated for verification of multi-processor cores, which interact with one another. These inefficiencies in current verification methodologies exacerbate time pressures and increase, significantly, the time-to-market, a key factor for developers and marketers of IC chips in being competitive in business.
To effectuate the growing trend towards SoC implementations of IC using multiprocessor platforms, SoC systems use tightly coupled software programs and processes running in independent peer processors. These independent execution units must be able to communicate with one another in a timely manner. However, in currently known implementations, communication is through mailbox/semaphore mechanisms to implement inter-process communication (IPC) protocols. Such mechanisms tend to be non-deterministic with respect to message delivery time, and are often not sufficient for real-time SoC functionality.
By way of example, and referring to FIG. 1, processors 1 through n communicate with each other through an on-chip chip bus arbiter, via a UIC (universal interrupt controller). The system of FIG. 1 additionally includes a single or multiple port memory controller and network controller in communication with the on-chip bus arbiter. In implementation, hundreds of cycles may pass before there is full data transfer between the processors (or other logic), thus impairing real-time communications. In the example of FIG. 1, processor 1 transfers data to processor “n” by first requesting authorization from the arbiter. Once this is granted, data is written into memory. Processor 2 polls the system and requests authorization from the arbiter to read the data from the memory. Once authorization is granted, processor “n” uploads the data for read operations. This same process would also occur for non-interrupt network controllers. This, of course, can take many hundreds of cycles to perform, taking into account the arbiters role of prioritizing data transfer between many devices.